In a conventional Type II phase lock loop frequency synthesizer, as shown in FIG. 1, the output frequency (fo) is equal to N times the reference frequency (fr). If we assume the loop is locked and stabilized when a frequency step (.DELTA.f) is introduced into the voltage controlled oscillator (VCO) the VCO will return to the correct frequency without cycle slipping. This is provided it is not exceedingly great. This frequency error--time relationship depends on the loop band-width and the damping factor.
In normal structures, if the feedback loop is open, and the VCO frequency is within the bounds of fo+.DELTA.f, the VCO will be pulled to fo without cycle slipping, as long as the proper initial conditions exist.
Often, it is desired to change the output frequency providing for frequency hopping. In this system, the division number N is changed, causing the VCO to hop frequency. In some systems the time between the time N is changed and the time (settling time) the frequency settles to within some specified error (fe) is important. Often it is desired and preferable that the settling time be as short as possible.
In an optimized loop the settling time is approximately inversely proportional to the reference frequency, (fr). The greater the reference frequency the less settling time necessary. Incrementing or decrementing N changes the output frequency fo by fr. Thus, the settling time would be inversely proportional to the channel spacing. The present systems are, however, handicapped to a certain extent, since it is the usual nature of the frequency divider that N must be an integer.